A conventional printed circuit board (PCB) includes a substrate of insulating material having upper and lower major surfaces, and electrical conductors in the form of conductive traces and/or pads on at least one of the major surfaces of the substrate. The conductive pads provide electrical contacts for electronic components to be mounted to the PCB and the conductive traces lead to and from the conductive pads. The electrical conductors are typically formed by forming a layer of conductive material, most notably copper, over an entire surface of the substrate, forming a mask on the conductive layer and which covers some portions of the conductive layer while exposing others, and etching the conductive layer using the mask to remove the portions of the conductive layer exposed by the mask.
Electronic components that are mounted to PCBs include passive electronic components such as resistors, capacitors, and inductors, as well as active electronic components such as integrated circuits (ICs). The electronic components are mounted to the PCB as supported by the substrate and electrically conductively connected to the conductive pads. The conductive traces leading to and from the pads serve to electrically connect the electronic components to each other and constitute what may be referred to as active traces of the PCB. That is, the active traces and the conductive pads form a circuit or part of a circuit along with various ones of the electrical components.
PCBs may be classified as single layer PCBs or multi-layered PCBs. Single layer PCBs have only one core layer and typically include conductive pads and active traces on only one side of the core layer (i.e., at the top of the PCB), and only conductive pads on the other side of the core layer (i.e., at the bottom of the PCB). Both single layer and multi-layered PCBs may have electrically conductive interconnects which electrically connect the conductive pads at different levels in the PCB. Thus, in the case of the aforementioned typical single layer PCB, the interconnects electrically connect the conductive pads and hence, the active traces, on one side of the PCB to the conductive pads on the other side of the PCB. In this case, the PCB can, in turn, connect the electronic components mounted to the PCB at the top thereof to an external electronic device by means of the conductive pads at the bottom of the PCB.
Multi-layered PCBs have been developed to meet the growing demand for more highly integrated electronic devices and for devices that provide greater numbers of functions. Conventional multi-layered PCBs include a stack of core layers each having a substrate and conductive traces (which may be referred to as “active” traces) and/or pads on each of the major surfaces of the substrate, and interposers disposed between vertically adjacent ones of the core layers. The interposers serve to space the core layers from each other in the stack and thereby separate conductive traces at the bottom of one of the core layers from the conductive traces at the top of an underlying core layer in the stack. To this end, the interposer may be a layer comprising a pre-preg.
Multi-layered PCBs thus allow for the conductive traces to be embedded in the stack, i.e., allow for greater numbers of interconnections to be provided than a single layer PCB within a given footprint.
Multi-layered PCBs are generally fabricated by laminating the core layers and interposers together in a stack, and then forming the interconnects by drilling a small hole (via hole) into the stack and then plating the surface that defines the via hole or filling the via hole with conductive material to electrically connect desired ones of the conductors of the core layers to one another. An interconnect that extends through the stack may constitute what is referred to as a through-via. An interconnect that extends through one side of the stack and ends within the stack may constitute what is referred to as a blind via.
One problem that can arise in the fabrication process is that the core layers are stacked in the wrong order. This can be very difficult to troubleshoot, especially using conventional DC testing, if it occurs on a middle one of the core layers whose major surfaces are covered and hence, whose conductors are not visible. In particular, if the core layers are stacked in the wrong order, then the vias will still connect to the correct internal traces, such that DC testing indicates proper connectivity. However, having the core layers out of order can cause dramatic errors related to trace impedances and/or greatly reduce the isolation between traces.
One proposed solution to this problem of detecting improper core layer sequencing, as shown in FIG. 1, is to create a “window” through the PCB from top to bottom in the form of a region clear of all conductors (i.e., the copper traces and pads) and in which “window” each core layer has an exclusive number (1-8 in this example) that identifies it. The number is printed in copper on a surface of the substrate of the core layer by the same process used to form the conductors on the surface. Furthermore, these numbers are offset within the window such that they are viewable from top and bottom. However, as FIG. 1 shows, the numbers become progressively obscured by the material of the various layers in the depth-wise direction of the PCB to the point where it becomes difficult to read the numbers identifying lower ones of the core layers. Also, some PCB material types are completely opaque, rendering the “window” ineffective.
Another common problem that occurs during the fabricating of a multi-layered PCB is a misalignment of the core layers. If the core layers are not aligned properly relative to each other (i.e., are mis-registered), albeit even slightly, then the vias may connect to the wrong trace on one of the substrates. When this occurs at a middle core layer, it can create a fault which is quite difficult to find. In the past, X-rays have been used to find these faults, but as PCBs and their conductors have been scaled down, the attainable resolution of the X-ray process imposes limits on the ability of the process to find the defect.
It is also possible to dissect the PCB to determine how accurately the internal layers are registered, but this is a time-consuming and destructive test.
A solution that overcomes these problems, as disclosed in U.S. Pat. No. 5,266,380, is the use of edge fiducial, reference or alignment marks associated with each of the core layers and which allow a determination to be made as to whether the core layers are registered properly and/or have been stacked in the proper order.
However, such fiducial, reference or alignment marks are still lacking in several respects and have not been used to their fullest potential in addressing some of the needs associated with PCBs and their manufacture.
What is needed, therefore, is a PCB that overcomes at least the shortcomings described above.